VLSI Testing and Design for Testability

Course Type: 
CEG
Code: 
7040
Level: 
Graduate
Credit Hours: 
3
Schedule Type: 
Lecture
Description: 

Design for testability of VLSI circuits. Topics include importance of testing, conventional test methods, built-in test, CAD tools for evaluating testability, test pattern generators and compressors, and test for mixed-signal systems and systems-on-a-chip (SOC). Department Managed Prerequisite(s): (Undergraduate level EE 4540 Minimum Grade of D and Undergraduate level EE 4540L Minimum Grade of D) or (Graduate level EE 6540 Minimum Grade of D and Graduate level EE 6540L Minimum Grade of D)

Corequisites: 

CEG7040L

Restrictions: 
Must be enrolled in one of the following Levels: Graduate, Medical, Professional.