Wright State University
CEG 360/560 - EE 451/651
Final Examination Review

Dr. Travis Doom

This document contains a list of topics and questions that could appear on the final examination in CEG 360. The majority of the final exam will cover the topics listed below, but any material appearing in the textbook readings or discussed in class may appear on the exam. Sample final examinations are not available. Questions on the final will be similar to those found in the half-hour examinations. Some questions will allow you to demonstrate your mastery of the material by allowing you to integrate material taught in various sections of the course. The best preparation for the final examination is to review your mistakes made on half-hour quizzes and to refresh your memory by reviewing the assigned reading.

1.

Given a digital device D with inputs X and outputs Y:

(a)

describe the function of D

(b)

formally present the function of D in terms of X and Y

(c)

find flip-flop input (excitation) and next-state (transition) equations

(d)

determine the next-state and output functions F and G

(e)

formally present the function of D as a state/output table

(f)

formally present the function of D as a state diagram

(g)

formally present the function of D as an ASM chart

(h)

draw a timing diagram from the state/output table

(i)

classify D as combinational, sequential Moore, or sequential Mealy

2.

Given a design specification for a clocked synchronous digital device (in English, as a state diagram, an ASM chart, transition list or a timing diagram):

(a)

build a state/output table from the specification

(b)

build a state diagram from the specification

(c)

produce an equivalent minimum state design

(d)

produce an equivalent minimum-risk design

(e)

choose a state variables assignments appropriate to the specification

(f)

produce a transition/output table

(g)

produce an excitation table and equations for state devices in the design

(h)

implement the design and draw an appropriate schematic with excitation logic, output logic, and appropriate state memory elements (D flip-flops, T flip-flops, J-K flip-flops, etc.)

(i)

implement the design ``ad-hoc''

3.

Given a state diagram:

(a)

discuss the function of the represented design

(b)

produce an equivalent diagram with or without transition expressions

(c)

minimize the diagram

(d)

identify errors or ambiguities in the diagram

(e)

produce an ASM transition list for the diagram

4.

Given a ASM chart:

(a)

discuss the function of the represented design

(b)

produce an ASM transition list for the chart

5.

Be familiar with fundamental timing issues common to sequential designs. Given a digital device D with timing information:

(a)

calculate its period, frequency and duty cycle of periodic signals

(b)

calculate the set-up and hold-times of the device or its sub-components

(c)

calculate the maximum clock frequency for the device

(d)

identify input combinations or timings for which the device will produce undefined (meta-stable or oscillating) behavior

6.

Be able to construct, recognize symbols for, provide characteristic equations for, provide timing for, discuss the advantages/disadvantages of, and produce designs utilizing common digital state devices, including:

(a)

Standard latches (D, S-R, /S-/R, S-R with enable)

(b)

Standard flip-flops (edge-triggered D, master/slave S-R, master/slave J-K, edge-triggered J-K, T)

(c)

Basic registers

(d)

Shift registers (serial in/out, parallel in/out, shift left/shift right/bidirectional, etc.)

(e)

Counters (asynchronous (ripple), synchronous serial, synchronous parallel, modulo-m, BCD, twisted-tail, ring, up/down, etc.)

7.

Be able to discuss the characteristics of a variety of memory devices:

(a)

What is programmable logic?

(b)

Why use programmable logic?

(c)

How are programmable logic devices programmed?

(d)

What are the characteristics of PLAs, PALs, GALs, ROMs?

(e)

What is ``memory''? Where and why is it used?

(f)

How is memory built internally?

(g)

How is memory organized and controlled in a system?

(h)

What are the characteristics of SRAM?

(i)

What are the characteristics of DRAM?

(j)

Be able to ``program'' the words of a memory device to perform a logic function

(k)

Why do large memory devices require two addresses (row and column)?

8.

Be able to discuss the associated costs and performance issues related to custom VLSI design, semi-custom VLSI design, and the FPGA approach to VSLI design

9.

Given a complex system:

(a)

Identify the partition between control and datapath

(b)

Identify the microoperations performed by the datapath

(c)

Identify the function of given control words, or visa-vera

(d)

Is the control hardwired? microprogrammed? non-programmable? programmable

(e)

Discuss the function of a basic RTL design for the system

10.

Relate the fundamentals of computer architecture:

(a)

What is the traditional functionality of a microprocessor? What is the current functionality of a microprocessor?

(b)

How are the microprocessors, its instruction set architecture, and compilers related? What are the cost vs. performance issues?

(c)

Describe the three basic types of computer instructions

(d)

How do computer instructions differ from microops?

(e)

Describe a pipelined instruction-execution cycle

(f)

What are pipeline hazards? Discuss common techniques for avoiding these hazards

11.

Describe the underlying philosophical differences between a CISC and RISC architecture?

(a)

What are the characteristics of each?

12.

Be able to define and discuss issues related to any terms introduced in the course, including:

(a)

Cost vs. Performance issues in digital design

(b)

Minimum Pulse Width

(c)

Finite Memory Machines

(d)

Asynchronous signals

(e)

Good design practice

13.

Expect one or more design problems on the final (similar to problems discussed during lecture or in course assignments)