VLSI Design Synthesis and Optimization Laboratory

Course Type: 
CEG
Code: 
7030L
Level: 
Graduate
Credit Hours: 
1
Schedule Type: 
Lab
Description: 

Required laboratory for EE 7530. Department Managed Prerequisite(s): (Undergraduate level EE 4620 Minimum Grade of D and Undergraduate level EE 4620L Minimum Grade of D) or (Graduate level EE 6620 Minimum Grade of D and Graduate level EE 6620L Minimum Grade of D)

Corequisites: 

CEG7030

Restrictions: 
Must be enrolled in one of the following Levels: Graduate, Medical, Professional.