VLSI Design Synthesis and Optimization

Course Type: 
CEG
Code: 
7030
Level: 
Graduate
Credit Hours: 
3
Schedule Type: 
Lecture
Description: 

VLSI Synthesis and optimization including data path synthesis, glue logic synthesis control-unit synthesis, and resource sharing. Covers behavioral level to layout level synthesis and corresponding algorithms. Department Managed Prerequisite(s): (Undergraduate level EE 4620 Minimum Grade of D and Undergraduate level EE 4620L Minimum Grade of D) or (Graduate level EE 6620 Minimum Grade of D and Graduate level EE 6620L Minimum Grade of D)

Corequisites: 

CEG7030L

Restrictions: 
Must be enrolled in one of the following Levels: Graduate, Medical, Professional.